VL25 输入序列连续的序列检测

 经典三段式：

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
	parameter[3:0] IDLE = 4'd0;
	parameter[3:0] S1 = 4'd1;
	parameter[3:0] S2 = 4'd2;
  	parameter[3:0] S3 = 4'd3;
	parameter[3:0] S4 = 4'd4;
	parameter[3:0] S5 = 4'd5;
	parameter[3:0] S6 = 4'd6;
	parameter[3:0] S7 = 4'd7;
	parameter[3:0] S8 = 4'd8;	

	reg[3:0] c_state,n_state;
	always @(*) begin
		case(c_state)
			IDLE: n_state <= a?IDLE:S1;
			S1: n_state <= a?S2:S1;
			S2: n_state <= a?S3:S1;
			S3: n_state <= a?S4:S1;
			S4: n_state <= a?IDLE:S5;
			S5: n_state <= a?S2:S6;
			S6: n_state <= a?S2:S7;
			S7: n_state <= a?S8:S1;
			S8: n_state <= a?S3:S1;
			default : n_state <= IDLE;
		endcase
	end
	always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            c_state <= IDLE;
        end
        else begin
            c_state <= n_state;
        end
    end

	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			match <=  0;
		end
		else if(c_state == S8 )begin
			match <=  1;
		end
		else begin
			match <= 0;
		end

	end
endmodule

循环移位检测：

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
    reg [7:0]    seq    ;
    always@(posedge clk&nbs***bsp;negedge rst_n)    begin
        if(!rst_n)    begin
                seq    <=    0    ;
                match  <=    0    ;
        end
        else begin
            seq    <=    {seq[6:0],a};
        end
    end
  
    always@(posedge clk )    begin
        if(seq == 8'b01110001)    
                match    <=    1    ;
        else
                match    <=    0    ;
    end
                
    
endmodule