VL26 含有无关项的序列检测

 

 

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

	reg [8:0] seq;
	
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			seq <= 0;
		else
			seq <= {seq[7:0], a};
	end

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			match <= 0;
		else
			casez(seq)
				9'b011_???_110: match <= 1;
				default: match <= 0;
			endcase
	end

endmodule